Toward scaling spin-based quantum processor with semiconductor technology

張鑑元 教授 - 國立清華大學電機系

Toward scaling spin-based quantum processor with semiconductor technology

張鑑元 教授 - 國立清華大學電機系

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日期

2024-05-20

時間

12:10-13:10

地點

理學教學新大樓物理系1F 36173會議室

領域

Quantum Information Science

講者

 張鑑元 教授 - 國立清華大學電機系

題目

Toward scaling spin-based quantum processor with semiconductor technology

摘要

This seminar explores the potential of building powerful quantum computers using spin qubits based on semiconductor technologies. We'll begin by introducing the fundamental concepts of spin qubit and the integration of spin qubits with photonic qubits, exploring their fundamental properties and potential applications. Secondly, we'll introduce walk through the recent advancements in single and two-qubit operations using single electron spin states. These demonstrations highlight the importance of material engineering and their critical role in building a large-scale quantum computing with spins.

The second part of the talk will provide a bird-eye view on the tailored Quantum Error-Correcting Codes (QECCs) for spin qubit-based processors. To unlock the full potential of spin qubits for large-scale processors, we'll investigate their performance with We'll focus on two specific distance-3 codes: the surface code and the Bacon-Shor code. We'll compare their performance using two encoding schemes: all Zeeman-type qubits and a hybrid scheme with Zeeman data qubits and singlet-triplet ancillary qubits. Our research demonstrates that the hybrid-qubit scheme offers a significant performance improvement (about 1 order of magnitude) compared to the all-Zeeman approach. These combined advancements in spin qubit technology and error correction strategies suggest a promising path towards building robust fault-tolerant quantum computers. The Bacon-Shor code with a hybrid qubit scheme appears to be a particularly strong candidate for achieving this goal.