Exponential Quantum Speedup in Boolean Matching for Reversible Logic Circuits
Prof. Jie-Hong Roland Jiang - Dept. of Electrical Engineering, NTU
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2026-10-05 12:10:00 ~
2026-10-05 13:10:00See event details for additional info.
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R36173, 1F, Dept. of Physics, Building of Science College, NCKU
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Exponential Quantum Speedup in Boolean Matching for Reversible Logic Circuits
Prof. Jie-Hong Roland Jiang - Dept. of Electrical Engineering, NTU
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DATE |
2026-10-05 |
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TIME |
12:10-13:10 |
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PLACE |
R36173, 1F, Dept. of Physics, Building of Science College, NCKU |
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FIELD |
Quantum Information Science |
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SPEAKER |
Prof. Jie-Hong Roland Jiang - Dept. of Electrical Engineering, NTU |
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TITLE |
Exponential Quantum Speedup in Boolean Matching for Reversible Logic Circuits |
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ABSTRACT |
Boolean matching is an important problem in logic synthesis and verification. Despite being well-studied for conventional Boolean circuits, its treatment for reversible logic circuits remains largely, if not completely, missing. This work provides the first such study. Given two (black-box) reversible logic circuits that are promised to be matchable, we check their equivalences under various input/output negation and permutation conditions subject to the availability/unavailability of their inverse circuits. Notably, among other results, we show that the equivalence up to input negation and permutation is solvable in quantum polynomial time, while its classical complexity is exponential. This result is arguably the first demonstration of quantum exponential speedup in solving design automation problems. Also, as a negative result, we show that the equivalence up to both input and output negations is not solvable in quantum polynomial time unless UNIQUE-SAT is, which is unlikely. This work paves the theoretical foundation of Boolean matching reversible circuits for potential applications, e.g., in quantum circuit synthesis. |
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